CACHE MEMORY MODELLING METHOD AND SYSTEM

The invention relates to a method for modelling a data cache memory of a destination processor, in order to simulate the behaviour of said data cache memory during the execution of a software code on a platform comprising said destination processor. According to the invention, the simulation is performed on a native platform having a processor different from the destination processor comprising the aforementioned data cache memory to be modelled, said modelling being performed by means of the execution, on the native platform, of a software code based on the software code to be executed on the destination platform, extended with information for modelling the behaviour of the data cache memory of the destination processor. The method of the invention comprises the following steps: the software code to be executed on the destination platform (101) is analysed (102) in order to identify basic blocks (104) of the code and a plurality of accessed variables in each block; annotations relating to the data cache memory to be simulated are added (106) to the code, said annotations comprising information for modelling the effect of the memory in the destination processor, thereby obtaining an annotated code (107); the annotated code is compiled (108); and the compiled annotated code is executed (109) together with a hardware model of the data cache memory. The step (106) in which the annotations relating to the data cache memory to be simulated are added to the code comprises the addition of information that can be used to obtain the addresses of the variables that the simulated data cache memory must access, in order to estimate if access to said variables will result in a cache hit or miss.