PACKET ROUTER FOR MULTIPROCESSOR SYSTEMS

The invention relates to a packet router for the interconnecting networks of a multiprocessor system. The router comprises 2·B basic building blocks (101, 102, 103, 104) arranged in a ring around a local node (100), wherein B is a natural number greater than 1. The router is configured such that each packet that enters the router flows through a loop that passes through the basic building blocks (101, 102, 103, 104) until it reaches an output port that directs same to its destination. Each basic building block (101) comprises a packet reception stage (RECEPTION), a packet ejection stage (EJECTION) and a FIFO buffer (DFIFO), in which the FIFO buffer (DFIFO) has two input ports (R3, Li) and two output ports (E3, Lo). One of the input ports (R3) is connected to an output of the packet reception stage (RECEPTION), while the other input port (L¡) is connected to an output port of a FIFO buffer of a front-end basic building block (104). Moreover, one of the output ports (E3) is connected to an input of the packet ejection stage (EJECTION), while the other output port (Lo) is connected to an input port of a FIFO buffer of a back-end basic building block (102). The FIFO buffer (DFIFO) is configured such that: either a packet leaves the router via the port (E3) connected to the packet ejection stage (EJECTION), or a packet leaves the FIFO buffer (DFIFO) via the port (Lo) connected to the aforementioned back-end basic building block (102) so that it can continue through the loop.